Job Description
To run & own AMS/MSV mixed signal simulations with Analog blocks as spice replacement for different combinations to validate the functionality with Logic and Analog together. Also, will be working on modelling Behavioral models for all the Analog blocks in HSIO IP and validate the same against CKT by driving a same stimulus.
Qualifications
Candidate should possess at least a Master of Science degree in Electrical Engineering or equivalent. Strong academic background required in Analog CKT and Digital design Hands on experience in any of the Mixed signal validation flows from Synopsys or Cadence 2 to 5 years of experience in Mixed signal validation and Behavioral Modelling of Analog CKT's The following preferred qualifications would be an added advantage: Familiarity with scripting languages like Perl and others . Good command on the Unix OS Experience running Analog simulations on critical blocks using any of the industry tools and capability to analyse and debug Experience on OVM or UVM is Appreciated
Inside this Business Group
IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.
Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
In certain circumstances the work model may change to accommodate business needs.
To run & own AMS/MSV mixed signal simulations with Analog blocks as spice replacement for different combinations to validate the functionality with Logic and Analog together. Also, will be working on modelling Behavioral models for all the Analog blocks in HSIO IP and validate the same against CKT by driving a same stimulus.
Qualifications
Candidate should possess at least a Master of Science degree in Electrical Engineering or equivalent. Strong academic background required in Analog CKT and Digital design Hands on experience in any of the Mixed signal validation flows from Synopsys or Cadence 2 to 5 years of experience in Mixed signal validation and Behavioral Modelling of Analog CKT's The following preferred qualifications would be an added advantage: Familiarity with scripting languages like Perl and others . Good command on the Unix OS Experience running Analog simulations on critical blocks using any of the industry tools and capability to analyse and debug Experience on OVM or UVM is Appreciated
Inside this Business Group
IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.
Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
In certain circumstances the work model may change to accommodate business needs.
