My Dutch semiconductor client pioneers ultra-efficient neuromorphic processors, crucial for IoT, wearables, and automotive domains.
I am recruiting an Analog/Mixed-Signal Verification Engineer who can enhance hierarchical verification for cutting-edge components.
Responsibilities will include but are not limited to:
- Generate, verify, and optimise behavioural models for analog blocks in mixed-signal verification.
- Implement event-driven modelling of analog circuits, conducting Model-vs-Schematic for SoC Verification handoff.
- Plan and coordinate analog/mixed-signal verification tasks.
- Conduct analysis, design, and verification simulations for block specifications.
- Document assigned blocks and actively participate in design review meetings.
I am looking for someone with some of the following experience:
- System-level modelling and simulation of analog and mixed-signal circuits.
- Basic understanding of SystemVerilog and assertions (preferred).
- Proficiency in scripting languages (Perl or Python).
- In-depth knowledge of circuit analysis, optimization, stress, and reliability analysis.
- Familiarity with Cadence Virtuoso AMS Designer Simulator tool flow (preferred).
Please get in touch with Parm Shergill for more information.
