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MTS Silicon Design Engineer

ONSITE FULL_TIME SENIOR_LEVEL
WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

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MTS SILICON DESIGN ENGINEER (LAYOUT DESIGN)

The Role

The SERDES Technology team designs high speed serial interface systems which are integrated into AMD devices. We are currently seeking an analog/mixed-signal layout engineer to join our world-class team.
THE PERSON:

You have a passion for highspeed analog mixed signal layout design, analog or digital on top chip integration and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

  • Physical design of analog mixed-signal from block level to top level integration and verification.
  • Chip level integration, physical verification and electricals closure 
  • Coordinate with cross-functional teams for debugging, yield improvement, and issue resolution. 
  • Contribute to layout process and methodology improvements and automation. 
  • layout design project lead role


PREFERRED EXPERIENCE:

  • At least ten years of highspeed analog or custom IC physical/layout design experience in FinFet technologies.
  • Good understanding of reliability concepts 
  • Good understating of layout electrical parameters and closure 
  • Hands-on experience using Cadence and Mentor tools is preferred 
  • Strong debug capabilities with parasitic extraction, LVS/DRC and other Physical verification checks. 
  • Sound knowlledge in Chip ESD and latch-up prevention technique 
  • Familiarity with circuit design concepts, flow and IC manufacturing processes 
  • Understanding of parasitic impact on circuit performance is a plus. 
  • Understanding of digital SOC flow is an advantage. 
  • Scripting Languages – Shell scripting, Python, TCL, PERL etc.
  • Ability to work across functions, level and remote sites 
  • Ability to work outside of official working hours ,if assigned, to support remote design teams is a plus


ACADEMIC CREDENTIALS:

  • Bachelors or Masters degree in computer engineering/Electrical Engineering 

LOCATION:

Singapore
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

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Location: Singapore, Singapore, Singapore
Company: AMD

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