Senior Engineer in Analog & Mixed Signal IC Design

Shanghai United Imaging Microelectronics Technology Co., LTD. ("UIM"), a subsidiary of United Imaging Healthcare Technology Group Co., Ltd., is the first domestic enterprise in China to independently develop high-end medical chips. The company is committed to the R&D of customized chips for all high-end medical devices, medical artificial intelligence chips and intelligent wearable medical chips. UIM also provides system solutions based on chips and specific applications. 

As the vision of "To be a world-class medical chip leader", UIM will take advantage of talent advantages to build a talent team covering the whole industry chain from chip R&D to packaging and production. The company will invest in the R&D of PET detector chip, ultra-high precision CT detector chip, DR flat analog front end chip, MR dedicated RF receiver link chip, ultrasonic dedicated AFE chip, wearable SOC chip and etc., focusing on providing overall solutions for the medical and health field. 

Location: Europe or Singapore

Job Description: 

 --Successful candidate will be responsible for the design, verification and debug tasks in state-of-the art ASICs for Health care related products. Candidate will work with the application and design team to establish the specifications for Analog Front End. Candidate will participate in the design and implementation of the building blocks (such as various types of data converters, low noise low power analog modules ) 

 --Candidate will involve in all phases of the ASIC development until product release, and post release support. 

Requirement:

 --Solid device physics (at the transistor level) is required. 

 --Solid knowledge in signal processing, noise analysis is required. 

 --Experienced in designing building blocks such as high performance op-amps, comparators，switched-cap circuits designs, low-power band gaps. 

 --Experienced in ultra-low power SAR, and high performance sigma-delta ADC design is a major plus. 

 --Experienced in high speed low power high performance data converters such as greater than 14 bits resolution and sampling rate more than several tens MHz is a plus. 

 --Experienced in whole chip ESD network planning and packaging consideration impacting chip performance is a plus. 

 --Experienced in creating analog layout and physical verification. 

 --Familiar with simulation techniques of switched-cap circuits to verify performance (noise, transfer function) 

 --Tools: well-fluent in industry standard IC design tools such as Cadence, and spice simulator 

 --Familiar with cadence layout tools 

 --Familiar with measurement equipment such as oscilloscope, jitter analyzer and other lab equipment. 

 --Strong inter-personal, teamwork and communication skills are required. Good English 

 --Self-motivated, Result oriented. 

 --PHD or Master degree in EE, more than 5 years industry experiences.