Job Responsibilities

Analog mixed-signal design verification lead.
Responsible for and perform chip level and sub-system level analog mixed signal design verification.
Drive analog mixed-signal design verification plan, methodology and best practice and guideline towards first silicon success.
Create and verify System Verilog (or equivalent) models, test benches, and automated verification simulations for mixed signal circuit blocks.
Work closely with system, analog, and digital team to understand and verify system and sub-system functions and specifications.
Communicate and follow through with design team to resolve issues found during verification.
Provide specification, design review and test requirements documentation to guide support team (system, application, ATE test engineers etc.) to meet design quality, yield and schedule targets.
Characterize, and de-bug designs in the lab and test platform for mass production as necessary.
Must be a team player and self-starter.

Main Requirements

MS degree in Electrical Engineering with 10+ or PhD degree with 8+ years of IC design verification or related experience.
Expert level experience and technical leadership in mixed signal design verification, UVM based DV, block level model specifications, simulation, system verilog real number modeling, writing checkers and assertions, customizing constraints, getting functional coverage collection using cover groups.
Extensive experience with system and modeling languages (MATLAB, RTL, SystemVerilog, SystemC, Verilog-AMS with wreal and poweraware).
Experience in modeling analog mixed-signal blocks such as bandgap, oscillator, bias network, amplifier, filters, analog/digital PLLs, ADC, DAC, LDO, and Class D AMP.
Expert level knowledge using common EDA tools and design verification methodology, such as Virtuoso, Incisive, Xcelium, Spectre, and SpectreX.
Extensive experience in creating test plan, scenarios and benches for mixed signal systems.
Ability to characterize and troubleshoot IC designs in the lab and ATE test floor.
Persevere to leave no stone unturned to make sure unexpected observations are root caused.
Outstanding communication and leadership skills.
Proficiency with digital design verification (including UVM) is a plus.
Class-D amplifier, PMIC, PLL and high performance sensor design verification background is a plus.

Senior Staff-Principal Analog Mixed-Signal Design Verification Engineer