Who we are:
Innatera is a rapidly-growing Dutch semiconductor company that develops ultra-efficient neuromorphic processors for AI at the edge. These microprocessors mimic the brain’s mechanisms for processing fast data streams from sensors, enabling complex turn-key sensor analytics functionalities, with 10,000x higher performance per watt than competing solutions. Innatera's technology serves as a critical enabler for next-generation use-cases in the IoT, wearable, embedded, and automotive domains.
Innatera's IC design team is responsible for the microarchitecture development and backend design of advanced neuromorphic processor ASICs. These chips combine mixed-signal processing elements with a highly-scalable digital architecture to realize energy-efficient AI capabilities in edge devices. The team is looking for an experienced, senior engineer to lead the backend ASIC design of Innatera's upcoming processor SoCs.
In this role, you will be responsible for:
- Owning and driving the execution of SOC designs from synthesis, floorplanning, place and route, timing signoff, physical signoff, and electrical signoff
- Defining and setting up the SOC top-level design template, integration of analog & digital IP blocks into the top-level design
- Collaborating closely with lead engineers to optimize designs, resolve issues, and achieve timing closure
- Establishing criteria to qualify IPs for integration into the top-level design
- Mentoring junior engineers and leading the team toward final tape-out
What you need to be successful in this role:
- MSc/PhD with 6+ years of relevant industry experience in backend/physical design of processor SOCs/IPs with multiple product tape-outs
- Strong timing analysis and debugging skills, generating constraints, lint cleaning
- Proven track record of implementing designs through the ASIC backend flow - synthesis, hierarchical, floorplanning, placement, CTS, routing, extraction, timing, physical verification,
- Proven experience with implementing designs with multiple voltage and clock domains, and/or low-power designs, CTS methodologies
- Strong experience with industry-standard EDA tool flows - Cadence/Synopsys
- Experience with scripting languages such as TCL, Perl, Python
- Experience in defining and setting up back-end tool flows
- Knowledge of SystemVerilog is a plus
- A goal-oriented attitude, problem-solving mentality, and is highly-motivated
- Be a self-starter, and passionate about technology
What do we offer :
- A dynamic working environment around a fearless culture
- Ambitious teams with the freedom to innovate
- A flexible working environment (work-from-home policy, flexible working hours, advantageous holidays scheme ..)
- An inclusive company culture that embraces communication, diversity, and support around holistic and personal development.
